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Baran Microelectronic GmbH

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V5ETHIO
V5ETHIO is an FPGA based process control board that allows rapid implementation and debugging of FPGA designs which performs data transfers over gigabit ethernet, USB 2.0 and optical fiber. It can control many external components through its input and output resources. V5ETHIO has also extensibility features that makes it suitable for a variety of systems.

Markets
  • Industrial
  • Telecom
  • Scientific
  • Test & measurement
  • Automotive

Applications
  • Data Transmission and Manipulation
  • Process control
  • Serial connectivity
  • Priniting
  • Digital Video
  • Maschine control
  • Bus Interface
  • High Speed Design
Features
  • Xilinx Virtex-5 LXT FPGA, XC5VLX30T-1FFG665C
    • XC5VLX50T FPGA and -2, -3 speed options are optional
    • Up to 46,080 logic cels
    • Up to 2,160 Kbit fast Block RAM
    • Up to 12 Digital Clock Managers (DCM)
    • Up to 6 PLLs
    • Up to 48 DSP slices
    • RocketIO GTP Low-Power Transceivers
    • 1x PCI Express Endpoint Block
    • 4x 10/100/1000 Ethernet MAC Block
    • On-chip battery powered module for design encryption
    • Built-in solution for thermal management
  • Xilinx XC95144XL-10TQG144C CPLD
    • Used for glued logic and IO extension
    • XC95288XL CPLD and -6, -7 speed options are optional
  • 1x Gigabit Ethernet port, RJ45 (supports 10/100/1000 Mbit, MII, GMII, SGMII)
  • 1x USB 2.0 peripheral control port
  • 2x SFP for fast optical fiber (SFP modules not included)
  • 4x SMA connected to RocketIO GTP Transceivers
  • 4x SMA connected to FPGA differential clock buffers
  • 2x Plastic optical fiber transmitters (Up to 70 Mbaud)
  • 2x Plastic optical fiber receivers (Up to 10 Mbaud)
  • DDR2 SDRAM (1 Gbit, up to 4 Gbit optional)
  • ZBT SRAM (9 Mbit, up to 72 Mbit optioanl)
  • Lienar FLASH (256 Mbit)
  • Serial EEPROM (256 Kbit)
  • Asynchronous SRAM (16 Mbit)
  • Programmable clock generator
    • 4.9kHz to 500MHz clock frequency
    • Generates reference clocks for Gigabit Ethernet, USB 2.0 and CPLD
    • Generates 2 differential and one single ended user clocks
  • Programmable super clock generator
    • 10.9-MHz to 1.175-GHz Frequency Range
    • Generates reference clocks for RocketIO GTP Transceivers
    • Generates 1 differential super clock for the FPGA
  • 100 MHz socketed user clock
  • JTAG Programming Interface for FPGA, Platform Flash and CPLD
  • Platform Flash to store FPGA configuration data
  • FPGA can also be configured over USB or Gigabit Ethernet
  • 2x 50 pin extension connectors (total 54 single ended IOs, matched length)
  • 1x 20 pin extension connector (total 13 single ended IOs)
  • 1x RS-232 Serial port
  • 6x RS-422 inputs
  • 4x RS-422 outputs
  • 4x potential free relays
  • 4x 24 volt relays
  • 12x 24 volt compatible optocoupler inputs
  • 4x 5 volt compatible optocoupler inputs
  • 4x potential free optocoupler outputs
  • 2x 10 bit, -10 to 10 volts digital to analog converters (12 bits optional)
  • 1x 10 bit analog to digital converter
  • Self recharching battery for design encryption
  • Dip switch & LEDs
  • 12 layer card with:
    • 50 Ohm impedance for single ended traces
    • 100 Ohm impedance for differential traces
    • Traces are routed with strict matched length rules
  • 230 x 230 mm dimensions
  • 5V power supply for logic
  • 24V power supply for optocouplers and relays



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